Responsibilities:
• Execute electrical, functional, & system tests of DDR5 and LPDDR5x memory sub-system test plans as part of a post silicon platform engineering team using hardware and software validation tools, oscilloscopes, and logic analyzers.
• Develop technical test plans and tools to support platform level silicon bring-up and the validation execution of DDR5 and LPDDR5x memory subsystem.
• Analyze & debug electrical and functional test data to drive into production SOC and system solution decisions.
• Supports lab functions including rework, inventory, & system test of platforms

Skills required:
• BS-EE / BS-CE / Masters plus at least 1 years directly related experience. An advanced degree will be considered a plus.
• Demonstrated technical expertise in the development and execution of platform level memory interface electrical and functional test plans
• Knowledge of PC architectures and system technologies.
• Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout design files
• Good written and oral communication skills, with the ability to communicate with a variety of engineering disciplines and management

Technical Skills:

CMOS/optical device analysis: SEM, AFM, RIE -cross section, top-down, layer to layer

Materials Analysis: film purity, adhesion, R&D, film properties (cmos/optical)

Thin Films, Implant, Diffusion, Etch, Spin Coating, device cross-section, prep/polish/catalog

Soldering, Troubleshoot-Repair- component, board and system level, signal tracing, fault isolation

Thermal Studies- Thermocouple of system, board, device -thermal data capture and analysis

Performance analysis- system, board, component, CPU/GPU, Memory, RMT, drivers, BIOS, OS.

Interpretation of schematics, block diagrams, PCB layout drawings

CPU, GPU, BIOS, UEFI, SI, fault isolation, root cause failure analysis, project management

Script editing: Python, Linux, Ruby, VMware, ssh, VB, PowerShell, Intel internal debug tools, c-scripts, RAS, power

profiles, CPU+memory firmware development, Persistent memory -ESXi development.

BIOS- QA validation- UEFI, platform/OS/driver compatibility

ISO17025 Laboratory Compliance, ISO9001 Manufacturing Compliance, 5S

UL 60950-1 safety standards, IPC-610 electronics quality standards

Audit preparation, technical report writing, Data collection, SPC, DOE

Lab infrastructure set-up and support of 14/15/16G persistent memory platforms.

Professional Summary:

Persistent Memory Engineering

Development and support of Storage Class Memory Solutions for 14/15/16G products from proofof- concept through to factory ship.

Continuous Integration of HW, FW, SW components for validation of enterprise products

Engineering analysis of development, factory and field defects via JIRA system.

Hardware- deployment, upgrade and validation of planar, CPU, memory, peripherals, PSU, SW defined memory,

PCIE products (CXL).

Fault isolation of platform functional and performance issues. In depth analysis of "corner case" defects requiring

subject matter expertise.

Component level rework, signal analysis, power characterization of special projects.

Software- Windows, MS PowerShell, Linux, VMware, python, UEFI, ssh, terminal emulator in development

environments.

Test case development - Define test criteria, variables and error injection for enterprise monolithic and modular

products.

Continuous support of test automation, tools and scripts.

Drive execution and status reporting of test cycles.

Confirm, triage and analyze all failures found in test.

Comprehensive analysis of BIOS, system logs and engineering test results.

Design and deployment of network infrastructure including Server + Network/client Systems.

Project management- document, equipment and product inventory control.

Lab infrastructure quality, safety and security compliance.

Graphics Engineering – PJM

Project management of high-end graphics OEM program

Validation of Functional and Thermal characterization of high-end graphics products.

Functional stress and thermal testing, system build up. (OS, BIOS, drivers, software/hardware)

Failure analysis, new product development and performance analysis of video products.

Defect Analysis –

Characterization of Samsung CMOS defects via scanning electron + atomic force microscopes (SEM, AFM).

Enterprise - sustaining engineering

Design and test of 12g modular server Intel facing products

Triage of all factory and customer failure issues

Complex experiments related to enterprise customer deliverables.

Energy use characterization of modular rack PDU’s

Network configuration and packet level performance of enterprise monolithic and modular systems.

Product Safety Engineering – Safety Engineering

L3 Root Cause Failure Analysis of Dell customer failures including Power products- PSU, Batteries, power Adapters

for Client, Enterprise and Workstation.

Validation of all aspects of Safety compliance - electrical, thermal, mechanical characteristics.

Vendor engagement regarding hazards in design issues.

Product Safety Engineering – UL Certification

Compliance Safety validation of all IT regulatory products to standardUL60950-1

Electrical Strength, Leakage, Input Current, Thermal testing, Mechanical Stability,

Flammability of materials- UL 60950-1 Signature certification

Engineering validation testing during UT, PT, ST phases of design

Laboratory support of all ISO17025 audit requirements. Technical writing- Document control, Engineering reports

and budget analysis.

Field Failure Analysis – Triage process

Failure Analysis of Power Edge Servers, Workstation and Desktop platforms.

Fault isolation of all aspects of system level functionality, component, chipset/device drivers, HW, FW, SW.

Drive field failures for trend fail analysis.

Collaboration with internal and external Engineering teams.

Comprehensive documentation of all technical conclusions.

Failure Analysis – field failures

Engineering Lead for Cisco Systems Route and Switch Catalyst 6K Network Products.

Technical liaison to Cisco Engineering.

Root cause failure analysis of network products with feedback into front-end manufacturing.

Vendor engagement of defect trends of Network products.

Diagnosis and validation of all field failures for Cisco Tier 1 customers.

Electro-optical device fabrication – Fab Startup

Analysis of coating and cure studies of multi-layer core/clad/core polymer films for optical device development team.

R&D of novel polymer materials.

Process dev of film Thk, uniformity, Purity, RI, adhesion of polymer on Si Via fill step coverage and IC reliability.

R&D of metal on polymer layers for delta control of refractive core clad propagation.

Spin coating Thk studies of novel polymer clad/core/clad material viability

Cross sectional device image analysis using S.E.M/ AFM.

Document control and report writing of all technical conclusions

Process Engineering – 150 mm

Lead Process Engineer - development and integration of Via tungsten fill process on Applied Materials

Centura PVD w/ etch back chamber. Equipment deployment, training and support.

Verification and characterization of existing step coverage of VIA fill on Varian 3290 metal deposition process

Production Support of Implant and Metallization manufacturing process control 150mm class 1 cleanroom

Process Engineering – 200 mm

Engineering Support, Statistical Process Control, Design of Experiments,

Process integration, Tool Installation, Thin film processes Al, Poly-Si, TiN, Ti, W films.

Implant characterization- B, Ph, As, including dopant drive-in via thermal anneal,

Equipment support including target and source changes, maintenance of wet processes.

Adjustment of tool characteristics to fine tune physical vapor deposition, Ion Implant,

etch and anneal processes to optimize thin film metals process in 200 mm fabrication facility.