JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and Client internal IP?s. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
EXPERIENCE AND EDUCATION: SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. Working knowledge of ARM cores and other I/O standard interfaces.
An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership
RTL, Verifications after IP design
Knowledge of Physical design
IP design, System Verilog
End to end design on cycle of a chip (SOC)
Would be working with cross functional groups
Scripting and automation would be done as the project continues
Top Skills:
Need 3/5 years of experience
Hardware design background
RTL Designs, Architectures, Micro Architectures
Can work with FPGA background as well
Experience in RTL design, Physical design, verifications (someone who has worked in a front end design team).
Scripting knowledge (Python, Perl, Shell)
