JOB DUTIES: Design and verify standard cell schematics. Port schematics into new technologies. Create new schematics for new functionality requirements. Verify circuit robustness using Monte Carlo simulation. Characterize standard cell libraries for custom PVTS. EXPERIENCE AND EDUATION: 5-7 years of relevant work experience; Experience with Schematic Design; Experience with Circuit Stimulation using Spice; Experience in Standard Cell Characterization using industry standard tools.
The candidate will be a member of the Memory I/O design team designing High Speed IO circuits and implementation of DDR IPs. The focus of the activity will be centered around spice simulations and other custom tools for analog/digital blocks.
The Person:
Good Circuit design fundamentals & scripting knowledge
Good knowledge of spice simulator and other custom tools like Totem, Nanotime etc
Effective communication skills
Good scripting knowledge
Responsibilities:
Run spice simulations for circuits that include Transmitter, Receiver – CTLE/DFE, DLL, DAC, OpAmp, Comparator and voltage regulators.
Work on tools and document best methods
Preferred Skilled Sets:
A successful track record in circuit design for High Speed IOs
Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
Ability to dig into RTL or FW code supporting the custom circuit implementation.
Education Requirements
Bachelors, Masters or PHD in EE or Comp. Eng
