The Analog/Mixed-Signal IP design team is looking for a Circuit Design Engineer to carry out the design and development for the next generation transceiver IOs, high-speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3, etc.), and chip-to-chip Gbps proprietary PHY IP solutions. As an Analog/Mixed-Signal Designer, your responsibilities include but not limited to the following:
1. Design and analyze mixed-signal circuit building blocks for PLL, DLL, and clock distribution to be used in the high-speed interfaces
2. Provide schematic layout guidance to mask designer and perform post-layout simulation
3. Pre-layout and post-layout design optimization to meet specifications across PVT, sensitivity, aging, electromigration simulation tests
4. Collaborate with layout engineers, RTL circuit designers to define IP sign-off requirements to ensure efficient IP integration
5. Define test plans and support for post-silicon IP bring-up, debug, validation, and characterization
6. Interface with SOC teams, system HW/SW teams, and global manufacturing teams to specify component level requirements

Experience in custom circuit design, and Transistor level design; Experience with physical design, directing layout engineers, performing electrical analysis checks (EM, noise), and fixing errors from said checks; Experience with SPICE simulations; Schematic and layout experience; Experience with Cadence, preferred; General knowledge of scripting and debugging; Experience with Perl, preferred; Languages: Verilog, C++/C, Perl, and Python, preferred; Processor custom circuit design, preferred; Experience with low power design, preferred; Problem solving skills, attention to detail, able to work individually and within a team