Design Engineer - Intermediate (US)
Santa Clara, CA 95054
Analog/mixed signal design and verification
Must solid experience with PLL design and clock distribution, and a desire to develop broader exposure to their downstream use in a dynamic, cutting edge VLSI Synthesis environment. This role will provide key support for multiple projects in a globally distributed team.
Responsibilities will include:
Read and understand documentation of specifications and answer end-user question regarding performance and analysis results.
Design the analog and custom digital portion of the PLL (filter, oscillator, frequency divider, PFD).
Understanding of tradeoffs between power consumption and performance.
Perform program management, tracking action items and progress against due dates.
EXPERIENCE AND EDUCATION:
Understanding of PLL and clock synthesis as well as VLSI design flow;
Experience in designing analog and mixed-signal circuits such as bias, amplifier, filter, VCO/ICO, high speed clock divider.
Familiarity with design and views of analog and mixed-signal circuits, e.g. Verilog, timing (.lib), LEF, GDS;
Familiarity with physical design verification, e.g. DRC and LVS;
Able to perform and interpret circuit simulations, e.g. using SPICE;
Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language