Hybrid Role in San Jose, CA
TOP MUST HAVE SKILLS:
1) Extensive power optimization experience in low power ASIC design
2) Proficiency in RTL design languages like Verilog or VHDL
3) Proficiency in programming languages like Perl, Python, and/or Ruby
4) Experience with power analysis tools like PowerArtist, PrimePower RTL and/or PrimeTime PX
We are seeking a power optimization engineer who has expertise in power optimization methodology to analyze and optimize pre-silicon IP RTL designs.
Key responsibilities:
- Implement the flow and methodology at the IP-level to align with the internal power optimization workflow for RTL power optimization
- Automate power data collection and track key power metrics through the development phases
- Support RTL and gate-level power rollup and analysis
- Work closely with design and implementation teams to analyze power data and identify power optimization opportunities
| Hours per Day | 8 |
| Hours per Week | 40 |
