The Role:

Testbench/Verification Engineer for the Infinity Fabric team. The Fabric IP is a flexible and scalable high-performance coherent interconnect used in multiple product lines.

The Person:

We are seeking an experienced testbench and verification engineer with exceptional programming skills, System Verilog and UVM experience, proven experience with working in complex testbench environments, and knowledge of the design verification cycles. Attention to detail, staying organized, tracking work to completion, excellent communication, analytical problem-solving skills, and connecting the dots in new initiatives are additional must-have skills. Experience in performance verification, performance debug and any kind of modeling is a highly valued plus. The engineer is expected to be comfortable working across geographies and timezones, to collaborate with multiple teams as needed.

Key Responsibilities:

• Develop, refactor and enhance UVM-based testbenches to verify or accelerate the simulation of complex designs at component or subsystem level.
• Work closely with other verification engineers, designers, architects, and performance engineers to understand and enhance the behavior of the test bench or related models. Perform tasks related to regression testing, debug and integration of any changes into the main codebase. Ensure optimal behavior of the testbench within the context of the block, chip and overall system.
• Execute test plans for constrained-random and directed tests, new checks and functional coverage
• Provide technical guidance and innovative ideas to improve quality, processes and productivity

Preferred Experience:

• Proficient in verification and testbench flows, especially seeking deep understanding and hands-on experience in System Verilog and UVM frameworks and testbenches, processes and flows.
• Proficient in debugging testbench and RTL code using simulation tools.
• Proficient in the use of Linux-based tools and scripting in Perl, Python and Ruby.
• Automating workflows in a distributed compute environment.
• Experience in approaches to simulation profile, efficiency improvement, acceleration.
• Development of reusable and maintainable code using software engineering best practices.
• Performance analysis, performance debug and modeling exposure are highly valued.
• Good working knowledge of SystemC and TLM with some related experience.
• Scripting language experience; Perl, Python, Ruby, Makefile